1. Field of the Invention
The present invention is relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a non-volatile semiconductor memory device.
2. Description of the Related Art
In a non-volatile semiconductor memory device like flash EEPROM and EPROM, high integration is very important. For this reason, various methods for the high integration of memory cells are studied.
Recently, as a memory cell of a small occupation area, a contactless memory cell is proposed in which a buried diffusion layer is used as a bit line, and a memory cell does not have a contact with the bit line. The contactless memory cell is described in, for example, a paper entitled "HIGH DENSITY CONTACTLESS, SELF ALIGNED EPROM CELL ARRAY TECHNOLOGY", (TECHNICAL DIGEST OF INTERNATIONAL ELECTRON DEVICES MEETING, 1986, pp. 592-595: conventional example 1), and Japanese Laid Open Patent Disclosure (JP-A-Heisei 6-283721: conventional example 2). In these conventional examples, it is disclosed that a bit line is composed of a diffusion layer and the surface of this diffusion layer is subjected to thermal oxidization. Here, the conventional example 1 is concerned with the contactless memory cell of a virtual ground array (VGA) structure and the conventional example 2 is concerned with the contactless cell of a NOR circuit structure.
The technique described in the conventional example 2 will be described below with reference to FIGS. 1A to 1G and FIG. 2. FIGS. 1A to 1G are cross sectional views of the manufacturing process of a memory cell section in order. These views are the cross sectional views of the memory cell section cut along a word line 116 which is shown in FIG. 2. FIG. 2 is an equivalent circuit diagram of an array structure of such memory cells.
As shown in FIG. 1A, field oxide films 102 are selectively formed on the surface of a P-type silicon substrate 101. Then, a protection insulating film 103 is formed on the silicon substrate in the area where the field oxide films 102 are not formed.
Next, as shown in FIG. 1B, a photo-resist mask 104 is formed in predetermined areas on the protection insulating film 103. Using the photo-resist mask 104 as an ion implantation mask, an N-type impurity such as arsenic ions is introduced by use of ion implantation. In this method, impurity introduction layers 105 are formed. Then, heat treatment is performed to activate the introduced impurity ions.
Next, as shown in FIG. 1C, the surface of the substrate is thermally oxidized so as to form buried diffusion layers 106. At this time, diffusion layer thermal oxidation films 107 are formed on the buried diffusion layers 106. This is because the N-type impurity introduction layers 105 are oxidized fast through the above thermal oxidation. As a result, the film thickness of the diffusion layer thermal oxidation films 107 becomes thicker than that of the other area. In this case, the diffusion layer thermal oxidation films 107 are formed to have the film thickness of about 100 nm.
Next, as shown in FIG. 1D, the protection insulating film 103 is removed and a first gate insulating film 108 is formed to function as a tunnel insulating film. The film thickness of this first gate insulating film 108 is about 10 nm. Then, a first polysilicon film 109 is formed to cover the first gate insulating film 108. Phosphorus impurity ions are doped in the first polysilicon film 109. Next, a second gate insulating film 110 is formed on the surface of the first polysilicon film 109. This second gate insulating film 110 is composed of a silicon oxide film, a silicon nitride film and a silicon oxide film (ONO). The film thickness of the second gate insulating film 110 is set to be in a range of 10 to 30 nm when it is converted to the film thickness of a silicon oxide film.
Next, as shown in FIG. 1E, photo-resist masks 111 are formed. Using the photo-resist masks 111 as etching masks, the first polysilicon film 109 is etched by use of a dry etching method to form first polysilicon films 109a in a strip manner.
Further, the N-type impurity such as arsenic ions is implanted by use of ion implantation to form an impurity introduction layer 112.
Next, the photo-resist masks 111 are removed. Then, heat treatment is performed, and then thermal oxidation is performed to form a buried diffusion layer 113. A diffusion layer thermal oxidation film 114 is formed on the buried diffusion layer 113 through this thermal oxidation. Also, a thick thermal oxidation film is formed on the sidewalls of the strip-shaped first polysilicon films 109a. These thermal oxidation films have the film thickness of about 100 nm.
Next, as shown in FIG. 1G, a second polysilicon film 115 is formed. Then, word lines are formed by use of a photolithography process and a dry etching process in subsequent steps. In the dry etching to pattern this word line, the dry etching is performed to the strip-shaped first polysilicon films 109a after the etching of the second polysilicon film 115. Thus, a floating gate electrode is formed.
In this method, using the buried diffusion layer 106 as a sub-bit line and the buried diffusion layer 113 as a sub-source line, a memory cell is formed to have a floating gate electrode which is formed between the sub-bit line and the sub-source line. In this case, the floating gate electrode extends to cross the buried diffusion layer 113 as the sub-source line and the buried diffusion film 106 as the sub-bit line and to cover the field oxide film 102. Therefore, the thick silicon oxide films which are formed on the buried diffusion layers 106 and 113 through the thermal oxidation, i.e., the diffusion layer thermal oxidation films 107 and 114 are important on the manufacturing process.
In the patterning of the floating gate electrode, the first polysilicon film 109 is patterned in the direction of the column direction, i.e., in parallel to the bit line to form the first polysilicon films 109a in a stripe manner. Then, the first polysilicon film 109 is patterned in the row direction, i.e., in parallel to the word line. Thus, the floating gate electrode is formed. This patterning in the row direction parallel to the word line is performed in a self-alignment manner with the word line as a control gate electrode by use of the etching. In this case, the diffusion layer thermal oxidation films 107 and 114 function as an etching stopper for the silicon substrate not to be etched, in the area where the polysilicon film is already removed by the patterning in the column direction. For this reason, the diffusion layer thermal oxidation films 107 and 114 are important on the manufacturing process.
Next, the array structure of such memory cells will be simply described.
As shown in FIG. 2, word lines 116 are connected to the control gate electrode of the floating gate-type transistor. Also, a main bit line 117 is arranged and a sub-bit line 118 is connected to this main bit line 117 via a MOS transistor. This sub-bit line 118 is composed of the above-mentioned buried diffusion film 106.
In the same method, a main source line 119 is provided and a sub-source line 120 is connected to this main source line 119 through a MOS transistor. This sub-source line 120 is composed of the above-mentioned buried diffusion layer 113.
However, in the method of manufacturing a contactless memory cell in such conventional technique, there is a limit in the forming of the memory cell by use of fine patterns so that the high integration of the non-volatile semiconductor memory device is difficult. The reason is that in the conventional technique, a silicon oxide film is formed on the buried diffusion layer through the thermal oxidation. For this reason, bird's beak, i.e., the extension of the silicon oxide film in channel direction of the floating gate-type transistor which is generated by this thermal oxidation constitutes a large bar of the fine processing.
Also, in such conventional technique, the estimation on the electric characteristic of the buried diffusion layer is difficult so that the circuit design is difficult. This is because the impurity ions in the buried diffusion layer are re-distributed through the thermal oxidation of the buried diffusion layer. That is, the diffusion layer containing impurity ions with a high concentration is oxidized fast and, at the same time, the impurity ions are piled up on the diffusion layer surface. For this reason, the electric resistance of the buried diffusion layer and the junction breakdown voltage between the buried diffusion layer and the silicon substrate can not be estimated.